小幫手訂正

Hi Minh, we have a urgent case and we need your help.

Now you are verifying FUSB343 + M31 eUSB2 PHY.

Could you help give the verification schedule for  "FOTG210 + M31 eUSB2 PHY solution" ?

The customer wants to know the schedule as soon as possible, please help.

 

以下為錄取的原因:

1.研究所的課程有實作的經驗 對於verilog的語法已經熟習 

2.筆試的題目成績-符合專業要求

3.現場測試其邏輯設計的程度 -符合專業要求

4.現場有測驗其閱讀SPEC的理解能力 -符合專業要求

Host write Doorbell in SSD to indicate commands are ready in Submission Queue

SSD fetches commands from Submission Queue

SSD write Completion Queue when command is finished

SSD generate interrupt to inform Host there are some events in Completion Queue

Host write Doorbell to inform SSD Completion Queue entry is released

Figure 3-1 illustrates the data structure of both the Submission Queue and the modified Submission Queue. For further details, please refer to the document security_filter_specification_V1_2.pdf

The software (SW) should modify the Submission Queue entry to the Modified Submission Queue format as shown below.

This operation will be performed when the SSD fetches a command from the Submission Queue.

This operation will be performed when the SSD writes completion queue entries.

Before these operations are activated, software (SW) should write the Sibling Submission Queue (SSQ) to the SSQ RAM, and the register files in the KEY REG block should be ready.

This operation will be used when the SSD fetches data from host memory. The Cadence PCIe IP will issue AXI read transactions to read data from host memory. Through this operation, the data being transferred over PCIe will be encrypted.

This operation will be used when the SSD writ

es data to host memory. The Cadence PCIe IP will issue AXI write transactions to write data to host memor

y. Through this operation, the data being transferred in the AXI write transaction will be decrypted.

"Step 1: When the CTRL block detects an AXI read command from the Cadence PCIe IP, it parses {QID, IDX, LBA Offset} from the AXI address.

Step 2: If {QID, IDX} are both "0", the CTRL block directs the AXI read data from the system AXI bus to the Cadence PCIe IP.

Step 1: When the CTRL block detects an AXI write command from the Cadence PCIe IP, it parses {QID, IDX, LBA Offset} from the AXI address.

Step 2: If {QID, IDX} are both "0", the CTRL block directs the AXI write data from the Cadence PCIe IP to the system AXI bus.

Step 1: When the CTRL block detects an AXI read command from the Cadence PCIe IP, it parses {QID, IDX, LBA Offset} from the AXI address.

Step 2: The CTRL block uses {QID, IDX} as SRAM addresses to fetch the SSQ entry.

Step 3: The CTRL block calculates the tweak using the "Starting LBA" of the SSQ entry and the "LBA offset" of the AXI address. It then parses the “KEYA/KEYB” bit of the SSQ entry and selects the appropriate register in the KEY REG block.

Step 4: If the “Algorithm BA416” bit of the SSQ entry is set to 1’b1, the CTRL block directs the AXI read data from the system AXI bus to BA416. If the "Algorithms BA425" bit is set to 1’b1, the CTRL block directs the AXI read data from the system AXI bus to BA425. When the “Encryption” bit of the SSQ entry is set to 1’b1, the CTRL block activates encryption.

Step 5: The CTRL block directs the encrypted data stream from the BA416 FIFO interface to the Cadence PCIe IP.

Step1. When CTRL detects an AXI write command from Cadence PCIe IP, CTRL parses 

{QID,IDX,LBA Offset} from AXI address. 

Step2. CTRL uses {QID,IDX} as SRAM address to fetch SSQ entry.

Step3. CTRL calculates tweak with “Starting LBA” of SSQ entry and “LBA offset” of AXI address. 

CTRL parses “KEYA/KEYB” bit of SSQ entry and selects the register in KEY REG block.

Step4.  If the “Algorithm BA416” bit of SSQ entry is 1’b1, CTRL directs the AXI write data of 

Cadence PCIe IP to BA416. If The “Algorithms BA425 bit” is 1’b1, CTRL directs the AXI 

write data of Cadence PCIe IP to BA425. When the “Decryption” bit of SSQ entry is 1’b1. 

CTRL activates the decryption.

Step5. CTRL directs the decrypted data stream of BA416 FIFO interface to system AXI bus.

Step 1: When the CTRL block detects an AXI write command from the Cadence PCIe IP, it parses {QID, IDX, LBA Offset} from the AXI address.

Step 2: The CTRL block uses {QID, IDX} as SRAM addresses to fetch the SSQ entry.

Step 3: The CTRL block calculates the tweak using the "Starting LBA" of the SSQ entry and the "LBA offset" of the AXI address. It then parses the “KEYA/KEYB” bit of the SSQ entry and selects the appropriate register in the KEY REG block.

Step 4: If the “Algorithm BA416” bit of the SSQ entry is set to 1’b1, the CTRL block directs the AXI write data from the Cadence PCIe IP to BA416. If the "Algorithms BA425" bit is set to 1’b1, the CTRL block directs the AXI write data from the Cadence PCIe IP to BA425. When the “Decryption” bit of the SSQ entry is set to 1’b1, the CTRL block activates decryption.

Step 5: The CTRL block directs the decrypted data stream from the BA416 FIFO interface to the system AXI bus.

Since we will stop the USB3.4 + eUSB2 verification, this version will not be delivered.

We do not know how the customer plans to use the USB 3.2 Gen2 controller. For this modification, we need to gather more information about the usage scenarios.

We suggest that the customer tie a constant value for the U2 PHY interface. However, we have not verified this application, so there are risks involved. 

We need to gather more scenarios about IP usage to better understand and mitigate these risks.

We have finished the verification phase for FUSB343 USB3.2 Gen2 controller. We will not to do the verification again

We have completed the verification phase for the FUSB343 USB 3.2 Gen2 controller, so we will not need to perform this verification again.

As mentioned previously, we only perform simulation and FPGA verification. We do not provide any other integration services.

Phase 3-1 provides the subsystem RTL, which can be used for your integration. We are not responsible for integration; we are only responsible for simulation and FPGA verification.

This is the top-level RTL for the subsystem, which includes the M31 PHY and the FOTG210 top module.

3-2. FOTG210 RTL source codes, subsystem top-level design, SDC constraints (FOTG210 only), datasheet, integration guide

3-3. Simulation test bench (with Synopsys VIP), user guide

We have delivered a temporary IP database to you. We are currently running the flow to check in the IP. Before March 3rd, we will deliver the final version to you.

Removing the USB2 controller is a significant update. We do not know how the customer uses the USB 3.2 Gen2 controller, so we need to gather more information about the usage scenarios."

"I have updated the response based on our conversation. The changes are underlined

Just use our sample Linux driver and our driver will handle HS/FS/LS transactions.

If you need help porting the driver to another platform, Faraday RD will fully support you.

If you need help porting the driver to another platform, our firmware RD team will fully support you."

FUSB343 uses the same AHB/AXI slave interface for both U2 and U3 functions.

Please note that the customer should be aware that U2 and U3 cannot be active simultaneously. FUSB343 will handle the U2/U3 switch functions.

What I want to emphasize is that FUSB343 can connect with both U3 PHY and eUSB2 PHY.

The customer will not see any internal blocks.

Please provide the diagram from the customer; we will help review it.

I found some issues have been resolved but their Jira tickets are still open. Could you please help close these Jira issues if they are indeed solved?

I need to update the report, so could you provide me with the following status for this week?

We will update this feature in the next release.

Since the data rate of A700 project does not exceed 2.5 Gbps, we do not have plans to update FTDSIH100 to version 2.5 in this release

Thank you for your explanation. Now we understand why you need 8 outstanding commands.

We need to estimate the schedule. Supporting 8 outstanding commands will take a longer schedule.

Could you accept supporting 4 outstanding commands instead? This would take a much shorter schedule.

The register highlighted in blue is inconsistent with the EHCI specification

 

 Hi Vegeta,

Regarding issue 1, please check the attached slide.

As previously discussed, we do not need to modify the EP number from 8 to 16.

The current design supports 8 IN and 8 OUT endpoints. We only need to add FIFO size.

Please double-check with Epson and help modify the description of the variables.

Thanks."

Attached is the temporary version of the datasheet.

Once the sfolder process is complete, we will provide you with the final version.

We will provide Option C.

VT/FTV is currently estimating the schedule.

Please await my response.

Hi Nam,

Could you please help expedite the response regarding the AXI4 feature schedule evaluation? 

T.H. has just followed up with me, and he mentioned that Kevin's team is also waiting for this schedule to arrange subsystem services for the customer.